发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT AND TEST METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which power consumption is low and a sure operation margin test can be performed and a test method for semiconductor integrated circuit. SOLUTION: In a normal time, a TEST flag signal is 'L', a switch SWA is turned on, a switch SWB is turned off, an output of a first boosting circuit 104 is supplied to a memory core 107 and a voltage drop power source 108. In a test time, a TEST flag signal is 'H', a switch SWA is turned off, a switch SWB is turned on, an external power source for test of which voltage is varied is connected to the memory core 107 through an external power source connection terminal 101, an output of a second boosting circuit 105 is supplied to the voltage drop power source 108. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003168298(A) 申请公布日期 2003.06.13
申请号 JP20010364685 申请日期 2001.11.29
申请人 FUJITSU LTD 发明人 MORI KATSUHIRO;FUJIOKA SHINYA
分类号 G01R31/28;G01R31/30;G01R31/317;G05F3/24;G11C11/401;G11C11/407;G11C29/50;(IPC1-7):G11C29/00 主分类号 G01R31/28
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