| 发明名称 |
MEMORY MASKING FOR PERIPHERY SALICIDATION OF ACTIVE REGIONS |
| 摘要 |
An integrated circuit memory fabrication process and structure, in which salicidation is performed on the periphery (and optionally on the ground lines) of a memory chip, but not on the transistors of the memory cells.
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| 申请公布号 |
US2003190781(A1) |
申请公布日期 |
2003.10.09 |
| 申请号 |
US20020305437 |
申请日期 |
2002.11.26 |
| 申请人 |
SGS-THOMSON MICROELECTRONICS, INC. |
发明人 |
HODGES ROBERT LOUIS;NGUYEN LOI NGOC |
| 分类号 |
H01L21/336;H01L21/60;H01L21/768;H01L27/105;(IPC1-7):H01L21/823;H01L21/320;H01L29/76 |
主分类号 |
H01L21/336 |
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