| 摘要 |
Disclosed is an improved register circuit of an extended mode register set. The register circuit comprises a first mode register block reset by a reset signal and outputting a predetermined level of signal in the input of an extended mode register set signal; a logic block for generating an output signal by OR operation of the reset signal and the mode register set signal and masking the mode register set signal when the predetermined level of signal is inputted from the first mode register block; and a second mode register block reset by output signal of the logic block.
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