发明名称 |
METHOD FOR FORMING POLYSIDE CONTROL GATE OF FLASH MEMORY DEVICE |
摘要 |
PURPOSE: A method for forming a polyside control gate of a flash memory device is provided to be capable of obtaining excellent profile of the control gate without the generation of an undercut phenomenon. CONSTITUTION: A gate oxide layer(102), a floating gate(104), and an inter-gate dielectric layer(106) are sequentially formed at the upper portion of a semiconductor substrate(100). A doped polysilicon layer(120) is deposited on the entire surface of the resultant structure. A polyside layer(140) is completed by forming a silicide layer(130) at the upper portion of the doped polysilicon layer. A hard mask(180) is formed at the upper portion of the polyside layer. The polyside layer is partially etched by supplying etching gas and nitrogen-containing gas using the hard mask as an etching mask.
|
申请公布号 |
KR20040019194(A) |
申请公布日期 |
2004.03.05 |
申请号 |
KR20020050535 |
申请日期 |
2002.08.26 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
PARK, JI YEON |
分类号 |
H01L27/115;(IPC1-7):H01L27/115 |
主分类号 |
H01L27/115 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|