| 摘要 |
<p>PURPOSE: A register controlled delay locked loop(DLL) is provided to reduce the number of required delay lines. CONSTITUTION: According to the register controlled delay locked loop(DLL), the first clock divider(21) generates a reference clock by dividing an internal clock. A delay line(23) inputs the internal clock. The second clock divider(24) divides the clock being output from the delay line. A delay model(27) reflects delay component of an actual clock path and an actual data path by receiving an output of the second clock divider. A phase comparator(22) compares a phase of an output signal of the delay model with a phase of the reference clock. And a delay controller(25) controls delay of the delay line in response to the comparison result of the phase comparator.</p> |
