发明名称 |
Latched sense amplifiers as high speed memory in a memory system |
摘要 |
A memory system includes a plurality of memory modules, each including at least one memory array. Each memory array has an associated line of sense amplifier latches, wherein each line of sense amplifier latches is activated independently. Each line of sense amplifier latches is capable of caching a row of data from the associated memory array. The capacity of each memory array and the number of memory arrays are selected such that a cache hit rate of over 90 percent is achieved for the memory system. |
申请公布号 |
US6717864(B2) |
申请公布日期 |
2004.04.06 |
申请号 |
US20020273442 |
申请日期 |
2002.10.15 |
申请人 |
MONLITHIC SYSTEM TECHNOLOGY, INC. |
发明人 |
LEUNG WING YU;HSU FU-CHIEH |
分类号 |
G06F12/16;G06F11/00;G06F11/10;G06F11/20;G06F12/06;G06F13/00;G06F13/40;G11C29/00;G11C29/04;G11C29/48;H01L21/66;H01L27/02;H04L5/14;H04L25/02;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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