Semiconductor memory device having a double data rate (DDR) mode and utilizing a plurality of comparison circuits to prevent errors due to a late write function

摘要

A semiconductor memory device having a double data rate (DDR) mode includes a first comparison logic circuit comparing the lower bits of a specified memory address for a reading operation with the lower bits of a specified memory address for a preceding writing operation, a second comparison logic circuit detecting if bits other than the lower bits match, and a third comparison logic circuit detecting that, when a match is obtained from the second comparison logic circuit, the lower bits of the specified memory address or a secondary memory address such as a burst address for the reading operation match the lower bits of the specified memory address or secondary memory address for the preceding writing operation. The device may have a late write function and a register may be provided to latch single data rate (SDR)/DDR mode information.