| 摘要 |
PROBLEM TO BE SOLVED: To shorten a TAT by appropriately associating an operation model with a high-order synthetic model (RTL model or the like) generated by submitting the operation model to high-order synthesis, in the functional verification of a semiconductor integrated circuit. SOLUTION: A semiconductor integrated circuit verification method includes a step for setting an observed variable for the operation model M1; a step for searching the operation model on the basis of the observed variable to extract a port for observation; a step which determines whether or not the extracted port for observation is an internal port, and if the port for observation is an internal port redefines the internal port into an external port; a step which generates an RTL model M2 by submitting the operation model to high-order synthesis while prohibiting logical compression for the observed variable; a step which extracts the signal change of the observed variable by performing a simulation for the operation model M1 to generate a reference model M3; and a step which compares the RTL model M2 with the reference model M3 on the basis of the observed model and outputs the comparison results. COPYRIGHT: (C)2004,JPO
|
