Standby mode circuit design for SRAM standby power reduction

摘要

This invention provides a new standby mode circuit design which reduces the power dissipation of static random access memory, SRAM circuitry. The circuit and method of this invention provides a reduced power supply voltage to SRAM memory cells so as to reduce the power dissipation of memory cells, while utilizing the full power supply voltage for the SRAM bit line and peripheral circuitry so as to preserve memory access performance.