| 摘要 |
PURPOSE: A delay locked loop circuit is provided, which is treated as a single product during production or test, by operating without regard to application field. CONSTITUTION: A clock buffer(210) stores an external clock and then outputs it. The first frequency divider(220) receives a clock signal from the clock buffer, and performs a frequency division operation with division number according to a division adjustment signal. A phase detector(230) detects a phase difference between a compensated clock signal and an output signal of the first frequency divider, and generates the first and the second comparison signal determining a delay step according to the comparison result, and generates a sample clock signal to sample the second comparison signal. A DLL control part(240) receives the sample clock signal and the second comparison signal. A delay line(250) receives the clock signal from the clock buffer, and receives the first and the second comparison signal, and shifts the clock signal to the right or left according to the first and the second comparison signal, and then outputs it as an internal clock signal. The second frequency divider(260) receives the internal clock signal, and performs a frequency division operation. And a replica part(270) compensates time difference between a clock from the external and an actual internal clock by receiving the internal clock signal, and generates the compensated clock signal and then outputs it to the phase detector.
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