| 摘要 |
PROBLEM TO BE SOLVED: To suppress a capacitive coupling between upper electrode wirings 5A, 5C, and a lower electrode wiring 4 and lower electrodes 2A-2D, without enlarging respective distances between cells 1A-1D, and between the cells 1A-1D and wiring 4, 5A-5D, in a capacity array comprising four unit capacity cells 1A-1D, and to enable enhancing thereby the relative precision of respective cells 1A-1D without causing the raise of a chip cost due to the degradation of relative precision and the increase of an area between the cells 1A-1D. SOLUTION: In the both sides of an upper electrode wiring 5A, a shielding wiring 6 is provided, which suppresses a capacity coupling between the upper electrode wiring 5A and the lower electrode wiring 4, and a capacity coupling between the upper electrode wiring 5A and lower electrodes 2B, 2C, respectively. Moreover, by extending the shielding wiring 6 to surround an upper electrode wiring 5C, a capacity coupling between the upper electrode wiring 5C and the lower electrodes 2A-2D are also suppressed. COPYRIGHT: (C)2004,JPO&NCIPI |
