| 摘要 |
PROBLEM TO BE SOLVED: To enhance machining precision of etching and to prevent an interconnect line to be exposed from being etched. SOLUTION: On the upper surface of a gate insulating film 10 composed of silicon oxide, gate insulating films 11, 12, 13 and an interconnect line 24 are formed of a metal, e.g. Mo, which can be etched by RIE dry etching using CF4 gas, or the like. An intermediate interlayer insulating film 14 of silicon oxide and an upper interlayer insulating film 15 of silicon nitride are then deposited on the upper surface thereof. Contact holes 16a, 17a, 18a and 26a are formed in the upper interlayer insulating film 15 by performing RIE dry etching using CF4 gas by using a resist pattern 39 as a mask. Subsequently, contact holes 16b, 17b and 18b are formed in the intermediate interlayer insulating film 14 and the gate insulating film 10 on polysilicon thin films 7, 8 and 9 by performing wet etching using BHF, and a contact hole 26b is formed in the intermediate interlayer insulating film 14 on the interconnect line 24. COPYRIGHT: (C)2004,JPO&NCIPI |
