| 摘要 |
A computer system wherein the FIS processor unit, as well as part, or all, of the FIS processor unit's support chips have been constructed in such a way as to shift the emphasis of design away from the use of logic gate technology (i.e. AND gates, OR gates, NOR gate and the like) and placing the said emphasis of design exclusively, or almost exclusively upon that of the use of a unique form of memory technology; i.e. specially designed mirco-memory circuits, to be called core memory circuits, that are then linked together to create a new form of lookup tables and a new form of memory-based finite state machines. That these new forms of lookup tables and memory-based finite state machines will be able to accomplish what, up to now, has been accomplished circuits composed of large numbers of logic gates: that of the carrying out all of the various functions necessary to accomplish all of the various instructions that compose the instruction sets of the present-day FIS microprocessors, be they specialized FIS processors or general-purpose FIS processors). In addition, this shift in the design and construction of FIS processor units and its support circuitry, be it specific or general, will allow a whole new range of instructions to incorporated into these new FIS processor unit. These new instructions will these said FIS processors to accomplish a wide new range of mathematical and algorithmic functions: instructions that are now not found in the instruction sets of any of the various present FIS processor units manufactured from a multiplicity of logic-gated circuits consisting of AND and/or OR gates, shift registers, flip-flops and the like. This expansion of the processor will allow the overall capacity of computer systems around these said FIS processors to expand substantially.
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