DYNAMIC CACHE REPLACEMENT WAY SELECTION BASED ON ADDRESS TAG BITS

摘要

A cache memory comprising: a mode input indicates in which of a plurality of allocation modes the cache memory is to operate; a set-associative array of entries having a plurality of sets by W ways; an input receives a memory address comprising: an index used to select a set from the plurality of sets; and a tag used to compare with tags stored in the entries of the W ways of the selected set to determine whether the memory address hits or misses; and allocation logic, when the memory address misses in the array: selects one or more bits of the tag based on the allocation mode; performs a function, based on the allocation mode, on the selected bits of the tag to generate a subset of the W ways of the array; and allocates into one way of the subset of the ways of the selected set.

主权项

1. A cache memory, comprising:
a mode input that indicates in which of a plurality of allocation modes the cache memory is to operate; a set-associative array of entries having a plurality of sets by W ways, wherein W is an integer greater than one; an input that receives a memory address comprising:
an index used to select a set from the plurality of sets; anda tag used to compare with tags stored in the entries of the W ways of the selected set to determine whether the memory address hits or misses in the array; and allocation logic that, when the memory address misses in the array:
selects one or more bits of the tag based on the allocation mode;performs a function, based on the allocation mode, on the selected one or more bits of the tag to generate a subset of the W ways of the array; andallocates into one way of the subset of the ways of the selected set.