发明名称 Timing control method for operating synchronous memory
摘要 A timing control method for operating a synchronous memory. The synchronous memory has a local data bus, a signal amplification bus and a global data bus. The timing control method includes manipulating the local data bus, the signal amplification bus and the global bus such that a series of operations including pre-charging the local data buses, developing signals on the amplifier buses is performed evenly within one clock cycle. Amplifying and transferring local data to global data is moved to next cycle and hid within the local data pre-charging period.
申请公布号 US6928013(B2) 申请公布日期 2005.08.09
申请号 US20030640348 申请日期 2003.08.12
申请人 ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. 发明人 CHANG CHIEN-YI
分类号 G11C7/10;G11C7/22;G11C8/18;(IPC1-7):G11C8/00 主分类号 G11C7/10
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