发明名称 |
METHOD OF FORMING VIA STRUCTURE AND METHOD OF FABRICATING PHASE CHANGE MEMORY ELEMENT MERGED OF SUCH VIA STRUCTURES |
摘要 |
PROBLEM TO BE SOLVED: To provide a method of forming a conductive plug structure such as a via plug using a multitude of conductive patterns and also to provide a method of fabricating a semiconductor element including a semiconductor memory element such as the method of fabricating a phase change memory element. SOLUTION: The method of forming an electrically conductive layer on a semiconductor substrate and further forming a via structure includes a process of forming a molding dielectric layer on the electrically conductive layer. Via holes are formed in the dielectric layer to expose partially the electrically conductive layer. Formation of a first via filling layer and partial removal of the formed layer yield formation of a preliminary via plug. The present invention provides a multilayer plug structure of a multilayer structure with via holes inscribed therein, which is formed by repeating the formation and removal of a phase change material layer, thereby reducing defects and damages as compared to a plug structure formed by a conventional method. COPYRIGHT: (C)2006,JPO&NCIPI
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申请公布号 |
JP2006060235(A) |
申请公布日期 |
2006.03.02 |
申请号 |
JP20050240283 |
申请日期 |
2005.08.22 |
申请人 |
SAMSUNG ELECTRONICS CO LTD |
发明人 |
LEE JANG-EUN;CHO SUNG-LAE;PARK JEONG-HEE |
分类号 |
H01L27/105;H01L21/28;H01L29/417;H01L45/00 |
主分类号 |
H01L27/105 |
代理机构 |
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