| 摘要 |
PROBLEM TO BE SOLVED: To provide a method for designing integrated circuits comprising a logical function circuit and a self-diagnosis circuit, wherein an error detection rate can be easily calculated, a node to be monitored can be easily optimized and a node cover rate is high. SOLUTION: The method comprises a first step S1 for composing test integrated circuits KT on the basis of a monitor node test list LM, a second step S2 for executing fault simulation and judging whether or not a toggle of each node can be detected by the self-diagnosis circuit KC, a third step S3 for calculating an error detection rate from the toggle detection possibility judgment result, and a fourth step S4 for judging whether or not the error detection rate is a standard error detection rate and more; wherein, when the error detection rate is less than the standard error detection rate, the monitor node test list LM is changed and processing is returned to the first step S1, and when the error detection rate is the standard error detection rate and more, the test integrated circuits KT are adopted to end the design of the integrated circuits. COPYRIGHT: (C)2009,JPO&INPIT
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