发明名称 Protection against access violation during the execution of an operating sequence in a portable data carrier
摘要 A method for protecting an operation sequence executed by a portable data carrier from spying out, wherein the data carrier has at least a processor core, a main memory and a cache memory with a plurality of cache lines. The processor core is able to access, upon executing the operation sequence, at least two data values, with the data values occupying at least one cache line in the cache memory and being respectively divided into several portions so that the occurrence of a cache miss or a cache hit is independent of which data value is accessed. A computer program product and a device have corresponding features. The invention serves to thwart attacks based on an evaluation of the cache accesses during the execution of the operation sequence.
申请公布号 US9589157(B2) 申请公布日期 2017.03.07
申请号 US201113581955 申请日期 2011.03.03
申请人 Giesecke & Devrient GmbH 发明人 Rempel Christof
分类号 G06F12/08;G06F21/79;G06F21/00;G06F21/71;G06F21/60;G06F21/55 主分类号 G06F12/08
代理机构 Workman Nydegger 代理人 Workman Nydegger
主权项 1. A method for protecting an operation sequence executed by a portable data carrier from spying out, wherein the data carrier has at least a processor core, a main memory and a cache memory with a plurality of cache lines (28.x), and wherein the processor core is configured to access, upon executing the operation sequence, at least two data values (v1, v2, . . . , vn, n≧2), the method comprising: providing said plurality of cache lines (28.x) and said at least two data values (v1, v2, . . . , vn, n≧2) such that the at least two data values (v1, v2, . . . , vn) occupy at least one cache line of said plurality of cache lines (28.x) in the cache memory, and each of said at least two data values (v1, v2, . . . , vn) are divided into several portions (vij); and providing, in each cache line of said plurality of cache lines (28.x) containing a portion (vij) of a first data value (vi), a portion (vkj) of every other data value (vk), such that for each cache line of said plurality of cache lines (28.x), the occurrence of a cache miss or of a cache hit is independent of whether the first or a different data value (vk) is accessed, wherein the portable data carrier is a smart card or a chip module.
地址 München DE