| 发明名称 |
COMPUTER ARCHITECTURE WITH RESISTIVE PROCESSING UNITS |
| 摘要 |
A processor includes an array of resistive processing units connected between row and column lines with a resistive element. A first single instruction, multiple data processing unit (SIMD) is connected to the row lines. A second SIMD is connected to the column lines. A first instruction issuer is connected to the first SIMD to issue instructions to the first SIMD, and a second instruction issuer is connected to the second SIMD to issue instructions to the second SIMD such that the processor is programmable and configurable for specific operations depending on an issued instruction set. |
| 申请公布号 |
US2017124025(A1) |
申请公布日期 |
2017.05.04 |
| 申请号 |
US201514928970 |
申请日期 |
2015.10.30 |
| 申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
Gokmen Tayfun |
| 分类号 |
G06F15/80;G06F9/38 |
主分类号 |
G06F15/80 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A processor, comprising:
an array of resistive processing units connected between row and column lines with a resistive element; at least one first single instruction, multiple data processing unit (SIMD) connected to the row lines; and at least one second SIMD connected to the column lines; a first instruction issuer connected to the at least one first SIMD to issue instructions to the at least one first SIMD; and a second instruction issuer connected to the at least one second SIMD to issue instructions to the at least one second SIMD such that the processor is programmable and configurable for specific operations depending on an issued instruction set. |
| 地址 |
Armonk NY US |
