发明名称 STORAGE SYSTEM AND CONTROL APPARATUS
摘要 A first control apparatus transmits, to a second control apparatus, a first error score based on an error detection situation at the time of accessing a first memory device through the second control apparatus, and transmits, to a third control apparatus, a second error score based on an error detection situation at the time of accessing a second memory device through the third control apparatus. The second control apparatus determines whether the first memory device malfunctions, based on a sum of a third error score based on the error detection situation at the time of accessing the first memory device and the received first error score. The third control apparatus determines whether the second memory device malfunctions, based on a sum of a fourth error score based on the error detection situation at the time of accessing the second memory device and the received second error score.
申请公布号 US2016321123(A1) 申请公布日期 2016.11.03
申请号 US201615080748 申请日期 2016.03.25
申请人 FUJITSU LIMITED 发明人 SAMPEI Akira;HANZAWA Fumio;SATO Hiroaki
分类号 G06F11/07;G06F3/06 主分类号 G06F11/07
代理机构 代理人
主权项 1. A storage system comprising: a first memory device; a second memory device; a first control apparatus; a second control apparatus; and a third control apparatus, wherein the first control apparatus includes: a first memory configured to store a first error score and a second error score, and a first processor configured to calculate the first error score on the basis of an error detection situation at a time of accessing the first memory device through the second control apparatus to store the calculated first error score in the first memory, calculate the second error score on the basis of an error detection situation at a time of accessing the second memory device through the third control apparatus to store the calculated second error score in the first memory, transmit the first error score to the second control apparatus at a predetermined time, and transmit the second error score to the third control apparatus at a predetermined time, wherein the second control apparatus includes: a second memory configured to store a third error score, and a second processor configured to calculate the third error score on the basis of an error detection situation at a time of accessing the first memory device to store the calculated third error score in the second memory, and determine whether the first memory device malfunctions on the basis of a sum of the first error score received from the first control apparatus and the third error score, wherein the third control apparatus includes: a third memory configured to store a fourth error score, and a third processor configured to calculate the fourth error score on the basis of an error detection situation at a time of accessing the second memory device to store the calculated fourth error score in the third memory, and determine whether the second memory device malfunctions on the basis of a sum of the second error score received from the first control apparatus and the fourth error score.
地址 Kawasaki-shi JP