| 摘要 |
A memory array employs individual variable threshold MNOS transistors as memory cells. A decoder employs a binary coded address signal to select a desired word in the memory. A decoder buffer translates the output of the decoder into the true or complement of the output signal of the buffer and places the resulting signal on the gate electrode of the variable threshold MNOS transistors constituting a given word line. A READ/WRITE contact receives a signal that determines the mode of operation of the memory. An input/output buffer at the end of each bit line in the memory array converts an input signal into an inhibit or WRITE signal in response to a control signal passed through a control section when the READ/WRITE circuit receives a signal suitable for switching the memory into the WRITE mode. If the signal on the READ/WRITE contact has switched the circuit into the READ mode, the input/output buffer serves to gate output current to exterior circuits. The control section also provides suitable substrate voltages to the memory array.
|
