SENDER PULSE TIMING CONTROL

摘要

The register-sender subsystem of a telephone switching system is of the type having common logic circuits including a wired program shared during cyclically recurring time slots by a plurality of register-senders, with each register-sender comprising a block of a common memory and having an associated register junctor serving as a peripheral unit for connection via a switching network to an outgoing trunk. The memory block for each register comprises a plurality of sets of storage elements including control sets and data sets which are accessed during sub-time slots. One of the control sets is a sender processor control set, which includes a timing store, a digit store, a dial pulse on-off control bit for controlling an outpulsing relay in the register junctor, and a multifrequency on-off control store for controlling a "time-on period" relay connecting a multifrequency sender output to the line. The timing store is used with common timing counters in the logic circuits for timing the pulse train generation for both dial pulse and multifrequency sending. Since the timing stores are in the individual memory of each register-sender, the pulse trains for different register-senders may be formed independently.