发明名称 |
Serializing transmitter |
摘要 |
In embodiments of a serializing transmitter, the serializing transmitter includes N multiplexing drive units, each configured to generate a series of output pulses derived from input data signals and multi-phase clock signals, and each multiplexing drive unit including a pulse-controlled push-pull output driver having first and second inputs and an output. Each multiplexing driver unit further includes a first M:1 pulse-generating multiplexer having an output coupled to the first input of the pulse-controlled push-pull output driver, and a second M:1 pulse-generating multiplexer having an output coupled to the second input of the pulse-controlled push-pull output driver, wherein each of the first and second M:1 pulse-generating multiplexers has three or fewer gate delays from a clock input to an output of the pulse-generating multiplexer. |
申请公布号 |
US9525573(B2) |
申请公布日期 |
2016.12.20 |
申请号 |
US201514604639 |
申请日期 |
2015.01.23 |
申请人 |
MICROSOFT TECHNOLOGY LICENSING, LLC |
发明人 |
Fiedler Alan S. |
分类号 |
H03K19/173;H04L25/49;H03K19/00;H03K19/0185 |
主分类号 |
H03K19/173 |
代理机构 |
|
代理人 |
Wisdom Gregg;Yee Judy;Minhas Micky |
主权项 |
1. A serializing transmitter, comprising:
N multiplexing drive units, each configured to generate a series of output pulses derived from input data signals and multi-phase clock signals, wherein N is a positive integer, and wherein each multiplexing drive unit includes
a pulse-controlled push-pull output driver having first and second inputs and an output,a first M:1 pulse-generating multiplexer having an output coupled to the first input of the pulse-controlled push-pull output driver and configured to generate a first series of intermediate pulses having a first pulse width at said output, where M is two or more, anda second M:1 pulse-generating multiplexer having an output coupled to the second input of the pulse-controlled push-pull output driver and configured to generate a second series of intermediate pulses having a second pulse width at said output,wherein each of the first and second M:1 pulse-generating multiplexers has three or fewer gate delays from a clock input corresponding to each of the multi-phase clock signals to an output of the respective pulse-generating multiplexer. |
地址 |
Redmond WA US |