High speed low voltage hybrid output driver for FPGA I/O circuits

摘要

A hybrid input/output pad driver includes an input node in a first voltage supply domain coupled to a p-device driver in the second voltage supply domain and an n-device driver in the second voltage domain. A p-channel pullup transistor is coupled between a voltage potential in a third voltage domain and an input/output pad. Its gate is coupled to the output of the p-device driver. An n-channel pulldown transistor is coupled between ground and the input/output pad. Its gate is coupled to the output of the n-device driver. An n-channel pullup transistor has a source coupled to the input/output pad, a drain coupled to the voltage potential in the third voltage supply domain. An inverter in the second voltage supply domain is programmably connectable between the output of the p-driver circuit and the gate of the n-channel pullup transistor.

主权项

1. A hybrid input/output pad driver for an integrated circuit comprising:
an input node; a pullup-device driver having an input and an output, the input coupled to the input node; a pulldown-device driver having an input and an output, the input coupled to the input node; a pullup transistor connected between a terminal to receive a voltage potential in a voltage supply domain external to the integrated circuit and an input/output pad, and a gate coupled to the output of the pullup-device driver; a pulldown transistor connected between a common potential and the input/output pad, and a gate coupled to the output of the pulldown-device driver; an n-channel pullup transistor having a source coupled to the input/output pad, a drain coupled to the terminal to receive the voltage potential in the voltage supply domain external to the integrated circuit, and a gate; and a programmable connection between the output of the pullup driver circuit and the gate of the n-channel pullup transistor.