2T-1R ARCHITECTURE FOR RESISTIVE RAM

摘要

A memory device includes a plurality of resistive memory cells and a plurality of word lines. Each resistive memory cell includes a resistive memory element, a first switching element electrically coupled in series with the resistive memory element, and a second switching element electrically coupled in series with the first switching element. The first switching element and the second switching element in each resistive memory cell is coupled to different ones of the word lines.

主权项

1. A method of operating an array of memory cells, each memory cell including a resistive memory element electrically coupled in series to a corresponding first transistor and to a corresponding second transistor, the first transistor including a first gate coupled to a corresponding one of a plurality of first word lines and the second transistor including a second gate coupled to a corresponding one of a plurality of second word lines, each memory cell coupled between a corresponding one of a plurality of bit lines and a corresponding one of a plurality of source lines, the method comprising:
identifying as a selected first word line, a selected second word line, a selected bit line, and a selected source line, respectively, the corresponding first word line, second word line, bit line, and source line for a first one of the memory cells that is selected for an operation; applying a corresponding word line voltage to the selected first and second word line based on the operation; applying a first bit line voltage to the selected bit line; boosting the first bit line voltage applied to the selected bit line to a second bit line voltage; and forming the resistive memory element corresponding to the first one of the memory cells in response to applying the word line voltage to the selected first word line.