发明名称 CIRCUIT FOR READING FERROELECTRIC MEMORY
摘要 A memory circuit has a ferroelectric memory cell having a word line and a bit line, an input transistor connected to the bit line, a gain element electrically connected the bit line, wherein the gain element includes a feedback capacitor, and an output terminal. A method of reading a memory cell includes applying a voltage to a word line of the memory cell, causing charge to transfer from the memory cell to a feedback capacitor, generating a voltage, amplifying the voltage by applying a gain having a magnitude of less than three, sensing an output voltage at an output node to determine a state of the memory cell, and storing the memory state in a latch.
申请公布号 US2016379703(A1) 申请公布日期 2016.12.29
申请号 US201514747679 申请日期 2015.06.23
申请人 Palo Alto Research Center Incorporated 发明人 SCHWARTZ DAVID ERIC;NG TSE NGA;MEI PING
分类号 G11C11/22 主分类号 G11C11/22
代理机构 代理人
主权项 1. A memory circuit, comprising: a ferroelectric memory cell having a word line and a bit line; an input transistor connected to the bit line; a gain element electrically connected the bit line, wherein the gain element includes a feedback capacitor; and an output terminal.
地址 Palo Alto CA US