发明名称 CIRCUIT, DRIVING METHOD THEREOF, AND SEMICONDUCTOR DEVICE
摘要 A circuit includes a current mirror circuit (CM circuit) including first and second transistors, a third transistor whose drain is electrically connected to a drain of the second transistor, a switch controlling the current output from the circuit, and first and second memory circuits. A reference current of the CM circuit is input to a drain of the first transistor; a current that is a copy of the reference current is output from the drain of the second transistor. When a current is output from the circuit, the reference current is not input to the CM circuit. A drain current corresponding to a voltage stored in the first memory circuit flows through the second transistor; a drain current corresponding to a voltage stored in the second memory circuit flows through the third transistor. The difference between the two drain currents corresponds to the output current of the circuit.
申请公布号 US2016379564(A1) 申请公布日期 2016.12.29
申请号 US201615183892 申请日期 2016.06.16
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 INOUE Hiroki;KUROKAWA Yoshiyuki;NAKAGAWA Takashi;AKASAWA Fumika
分类号 G09G3/3241 主分类号 G09G3/3241
代理机构 代理人
主权项 1. A circuit comprising: an output terminal; a current mirror circuit comprising a first transistor and a second transistor; a third transistor; a switch; a first memory circuit; and a second memory circuit, wherein a first voltage is input to a first terminal of the first transistor and a first terminal of the second transistor, wherein a second voltage is input to a first terminal of the third transistor, wherein a reference current is input to a second terminal of the first transistor, wherein a second terminal of the second transistor and a second terminal of the third transistor are electrically connected to each other, wherein the switch is configured to control an electrical connection between the second terminal of the second transistor and the output terminal, wherein a third voltage stored in the first memory circuit is input to a gate of the second transistor, and wherein a fourth voltage stored in the second memory circuit is input to a gate of the third transistor.
地址 Atsugi-shi JP