发明名称
摘要 <p>A capacitive read only memory operable to respond to the logical product of the inputs to the memory. The read only memory consists of a pair of plates or memory planes capacitively coupled together. Circuitry logically inverts the input pulses to the first plane and selective capacitor placement creates pulsing on all outputs from the second plane except on the desired output. Circuitry logically inverts the pulses from the second plane resulting in an output which is the logical product of the input signals.</p>
申请公布号 JPS4952544(A) 申请公布日期 1974.05.22
申请号 JP19730066296 申请日期 1973.06.12
申请人 发明人
分类号 G11C17/04;(IPC1-7):G11C17/00 主分类号 G11C17/04
代理机构 代理人
主权项
地址