Passivation layer topography

摘要

A topographical structure is formed within an integrated circuit (IC) chip passivation layer. The topographical structure includes a trench extending below the top surface of the passivation layer and above the top surface of an uppermost inter-metallic dielectric layer underlying the passivation layer associated with the uppermost wiring line of the IC chip. The topographical structure may also include a ridge above the top surface of the passivation layer along the perimeter of the trench. The topographical structure may be positioned between a series of IC chip contact pads and/or may be positioned around a particular IC chip contact pad. The topographical structures increase the surface area of the passivation layer resulting in increased underfill bonding to the passivation layer. The topographical structures also influence capillary movement of capillary underfill and may be positioned to speed up, slow down, or divert the movement of the capillary underfill.

主权项

1. A method to fabricate an electronic package comprising:
depositing a passivation layer upon an upper inter-metallic dielectric layer of an integrated circuit (IC) chip; forming a topography structure within the passivation layer, wherein the topography structure comprises a trench of a depth less than the passivation layer thickness and a ridge raised above the passivation layer about the perimeter of the trench, and; bonding the IC chip and the external circuitry with underfill between the external circuitry and the passivation layer.