发明名称 |
SYSTEM, METHOD OF EXECUTING A PLURALITY OF THREADS INCLUDED IN A COMPUTER PROGRAM BY CIRCUITRY, AND ONE OR MORE NON-TRANSITORY COMPUTER-READABLE MEDIUM |
摘要 |
A system includes circuitry configured to execute a first thread of a plurality of threads, measure an execution time period during which the circuitry executes the first thread without executing other threads of the plurality of threads, determine whether the measured execution time period exceeds a threshold value, specify first address information of a first instruction which is included in the first thread when it is determined that the measured execution time period exceeds the threshold value, the first instruction being an instruction that is scheduled to be executed, exchange the first instruction stored in an address region specified by the first address information with a second instruction instructing the circuitry to switch from executing the first thread to executing a second thread of the plurality of threads, and switch from executing the first thread to the executing the second thread by executing the second instruction. |
申请公布号 |
US2016328232(A1) |
申请公布日期 |
2016.11.10 |
申请号 |
US201615139991 |
申请日期 |
2016.04.27 |
申请人 |
FUJITSU LIMITED |
发明人 |
TAMURA Yuto;NAKASHIMA Kohta |
分类号 |
G06F9/30;G06F9/32 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
1. A system configured to execute a plurality of threads included in a computer program, the system comprising:
circuitry configured to execute a first thread of the plurality of threads, measure an execution time period during which the circuitry executes the first thread without executing other threads of the plurality of threads, determine whether the measured execution time period exceeds a threshold value, specify first address information of a first instruction which is included in the first thread when it is determined that the measured execution time period exceeds the threshold value, the first instruction being an instruction that is scheduled to be executed by the circuitry, exchange the first instruction stored in an address region specified by the first address information with a second instruction instructing the circuitry to switch from executing the first thread to executing a second thread of the plurality of threads, and switch from executing the first thread to the executing the second thread by executing the second instruction. |
地址 |
Kawasaka-shi JP |