| 摘要 |
This relates to a predetection maximal ratio digital diversity combiner for a phase shift keyed digital data signal propagating on N different paths through a dispersive medium, where N is an integer greater than one. Each of N signal channels respond to the data signal propagated on a different one of the N different paths. Each of the channels include an arrangement to separate the data signal into an inphase component and a quadrature component and also a pair of analog-to-digital converters to convert the inphase component into an inphase digital signal and the quadrature component into a quadrature digital signal. A digital adder arrangement is coupled in common to the output of each of the N channels to digitally add the inphase digital signal of each of the channels together to produce a combined inphase digital signal and to digitally add the quadrature digital signals of each of the channels together to produce a combined quadrature digital signal. A decision circuit responds to the most significant digit of both the combined inphase digital signal and the combined quadrature digital signal to recover the data conveyed by the data signal. A clock recovery circuit responds to the combined inphase digital signal, the combined quadrature digital signal and the recovered data to produce properly phased timing signals for control of the decision logic, each of the analog-to-digital converters and an automatic gain control circuit common to each of the N channels. Each of the channels further include an arrangement coupled between the associated pair of analog-to-digital converters and the digital adder arrangement and also to the decision circuit. This arrangement is responsive to the recovered data and the inphase and quadrature digital signals to determine the maximal ratio weights of these signals. The determined inphase and quadrature digital weight signals are employed to weight the inphase digital signal and the quadrature digital signal prior to digitally adding thereof in the adder arrangement. An automatic gain control circuit is coupled to the last mentioned arrangement of each of the channels and to the clock recovery circuit to produce an automatic gain control signal to control the gain of the data signal in each of the channels. This is accomplished by detecting the maximum maximal ratio weight of either the inphase or quadrature digital signal of any of the channels involved in the diversity combiner and generating from this maximum maximal ratio weight an automatic gain control voltage. |
