System for generation of a synchronization signal via stations connected via a packet switching network

摘要

The present invention relates to the domain of synchronization of items of equipment connected by a packet switching network. It relates more specifically to a system for generation of a synchronization signal (PIPA, PIPB) and a clock signal (CLK_outA, CLK_outB) by a slave station (SA, SB) connected to a master station (SM) via a packet switching network. The master station (SM) is conformed to produce a master clock signal (CLKM) of frequency FM and a master synchronization signal (PIPM). The master synchronization signal (PIPM) is in phase with the master clock signal (SM). The slave station (SA, SB) comprises the primary synthesis means (SM1A, SM1B) producing a slave periodic signal TICKSA, TICKSB), the periodic signal (TICKSA, TICKSB) is in phase with the master clock signal (CLKM). According to the invention, the slave station (SA, SB) also comprises the secondary means of synthesis (SM2A, SM2B) to synthesize a clock signal (CLK_outA, CLK_outB) and the synchronization signal (PIPA, PIPB) and in that said clock signal (CLK_outA, CLK_outB) and said synchronization signal (PIPA, PIPB) are in phase with said signal (TICKSA, TICKSB).

主权项

1. A slave station apparatus comprising:
a phase-locked loop comprising a filter, a configurable oscillator; and a first stage frequency divider; a second stage frequency divider; a counter; and circuitry configured to: detect a master clock signal of frequency FM and a master synchronization signal received from a packet switching network, wherein said master synchronization signal is in phase with the master clock signal; produce, using the second stage frequency divider, a slave periodic signal, wherein said slave periodic signal is in phase with the master clock signal and the slave periodic signal is of frequency FM/p where p is an integer; generate a slave clock signal identical to the master clock signal; detect the slave clock signal produced by the second stage frequency divider; detect, using the phase-locked loop, the slave periodic signal; generate, using the configurable oscillator, a clock signal having a frequency F that is in phase with the slave periodic signal detect, using the first stage frequency divider, the clock signal having the frequency F that is in phase with the slave periodic signal; produce, using the first stage frequency divider, a local periodic signal of frequency F/q where q is an integer; detect, using the counter, the clock signal having the frequency F that is in phase with the slave periodic signal; send, via a decoder, a video synchronization signal; initialize, using the counter, the video synchronization signal based at least partially on a first stage initialization signal in phase with the slave periodic signal; compare the local periodic signal and the slave periodic signal using the phase locked loop so as to produce a comparison result; detect the comparison result with the filter; and generate, using the filter, a filtered result and send the filtered result to the configurable oscillator, the first stage initialization signal being the local periodic signal.