| 摘要 |
A logic detect circuit chip is mounted on a substrate having a plurality of first conductors on one surface connected to first inputs of respective bit-gates of the logic circuit, and a plurality of further conductors on the same surface connected to the other inputs of respective bit-gates. The further conductors are traversed by at least one bus conductor on the other surface of the substrate. The further conductors are selectively connectible to each bus conductor by conductive slugs at the crossing points. The bus conductor and the first conductors are connectible respectively to a 0 volt reference line and a parallel binary transmission line. By appropriate selection of the slug connections between further conductors and the bus line the detect circuit may be associated with a particular binary number on the transmission line. Two bus lines may be used, connected respectively to 0 volts and a different voltage reference. The slug connections are suitably made at all cross-over points during manufacture for selective removal to "code" the circuit before use. |
