| 发明名称 |
MEMORY DEVICE WITH REDUNDANT IO CIRCUIT |
| 摘要 |
A device includes input/output (IO) circuits, a redundant IO circuit and a redundant IO control unit. The input/output (IO) circuits coupled to a memory array. The redundant IO circuit is coupled to the memory array and the plurality of IO circuits. The redundant IO control unit is coupled to the IO circuits and the redundant IO circuit. In response to a failure column address signal, the redundant IO control unit configures the redundant IO circuit to substitute a failed IO circuit of the IO circuits. The redundant IO control unit includes a storage circuit, and during a shutdown mode, the storage circuit is configured to store the failure column address signal. |
| 申请公布号 |
US2016293277(A1) |
申请公布日期 |
2016.10.06 |
| 申请号 |
US201615076416 |
申请日期 |
2016.03.21 |
| 申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
KATOCH Atul |
| 分类号 |
G11C29/00;G11C29/04 |
主分类号 |
G11C29/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A device, comprising:
a plurality of input/output (IO) circuits coupled to a memory array; a redundant IO circuit coupled to the memory array and the plurality of IO circuits; and a redundant IO control unit coupled to the IO circuits and the redundant IO circuit, wherein
in response to a failure column address signal, the redundant IO control unit configures the redundant IO circuit to substitute a failed IO circuit of the IO circuits, andthe redundant IO control unit comprises a storage circuit, and during a shutdown mode, the storage circuit is configured to store the failure column address signal. |
| 地址 |
HSINCHU TW |
