| 摘要 |
A memory circuit including one-transistor-per-bit memory cells arranged in a matrix array of m and n columns, one capacitor, and n differential amplifiers associated with the n respective column. The memory array is divided into first and second row groups and each differential amplifier has a first input terminal connected to memory cells belonging to the first row group and associated with one of the n columns and a second input terminal connected to memory cells associated with the second row group and connected to the same column that is connected to the first terminal. The memory circuit also includes an output amplifier having two input terminals, a plurality of first and second switching means associated with respective columns and controlling means for controlling the first and second switching means. The first and second switching means, associated with the same column may be selected and controlled by the same controlling means.
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