| 摘要 |
PURPOSE:To attain the improvement of speech quality and a decrease in error rate by arranging shift registers for the write control of input PCM signals and by allowing them to be an elastic storage and series-parallel converter circuit. CONSTITUTION:Frame synchronous circuit 18 detects the frame synchronizing position of a time-division multiple PCM signal, shift registers 20 23 are provided which has a number of bits equivalent to the word length of the signal, and the phase of a write clock to registers 20 23 is compared 23 with that of a switching signal sequentially changing over paralleled outputs of registers 20 23. Corresponding to its result, it is decided through write control 19 whether a word of fixed codes in the PCM signal should be written to the 1st and 2nd registers at the same time and the following word should be written to the 3rd register or the following words should be written skipping over the word to be written to the 1st register. Namely, registers 20 22 are used as both an elastic storage and series-parallel converter, thereby realizing the improvement of speech quality and a decrease in error rate. |
