发明名称 |
Unequalized clock data recovery for serial I/O receiver |
摘要 |
A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error signals to adjust the receiver portion, a phase feedback mechanism separate from the equalization feedback loop to provide a phase error, and a clock data recovery block coupled to receive the phase error to perform timing recovery for the receiver portion independent of the equalization feedback to adjust the sampling. |
申请公布号 |
US9479364(B2) |
申请公布日期 |
2016.10.25 |
申请号 |
US201514711259 |
申请日期 |
2015.05.13 |
申请人 |
Intel Corporation |
发明人 |
He Yun;Sarkar Sanjib;Deng Fei;Singaravelu Senthil Arun;Nagulapally Narender;Shah Pranali |
分类号 |
H04L25/03;H04L7/00;G06F13/40;H04L7/033;H04L7/027 |
主分类号 |
H04L25/03 |
代理机构 |
Schwegman Lundberg & Woessner, P.A. |
代理人 |
Schwegman Lundberg & Woessner, P.A. |
主权项 |
1. An input/output receiver comprising:
a receiver portion to receive an analog differential serial input and sample the analog differential serial input to provide data and error signals; an equalization feedback loop responsive to the data and error signals to adjust the receiver portion; a phase estimator responsive to the data and error signals to estimate an unequalized phase error, wherein the phase estimator is not subjected to the equalization feedback loop; and a clock data recovery circuit coupled to the phase estimator to perform timing recovery for the receiver portion. |
地址 |
Santa Clara CA US |