发明名称 STATIC TYPE MIS MEMORY
摘要 PURPOSE:To reduce the power consumption at a static type MIS memory write time by using the series circuit of an enhancement type MISFET and a depletion type MISFET for the load of a digit wire. CONSTITUTION:The series circuit of enhancement MISFETQ2 and Q2' which have gates connected to power source Vcc as a load between a pair of digit wires Dm and Dm' of the static type MIS memory composed of MISFET's and depletion type MISFETQ2 and Q2' which have gates connected to sources is used. Thus, MISFETQ1 and Q1' have a high impedance characteristic and a low impedance charactristic in the low voltage region and in the high voltage region respectively. Meanwhile, FETQ2 and Q2' have the reverse impedance characteristics. Consequently, by the load characteristic of this series circuit, the power consumption can be reduced while securing the large current at a read time.
申请公布号 JPS54113222(A) 申请公布日期 1979.09.04
申请号 JP19780019833 申请日期 1978.02.24
申请人 HITACHI LTD 发明人 ITOU TSUNEO;SAITOU TAKESHI
分类号 G11C11/41;G11C11/412;G11C11/419 主分类号 G11C11/41
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