| 摘要 |
PURPOSE:To obtain a transistor circuit where the external supply voltage is low and a high-speed low-consumption power signal response is obtained. CONSTITUTION:The first inverter circuit is constituted by the first depletion- type load MOSFETQL1 and the first enhancement-type driving FETQD1, and the second inverter circuit is constituted by FETQL2 and QD2 similarly. Gate electrodes of FETQL1 and QL2 are connected to output end A commonly, and gate electrodes of FETQD1 and QD2 are connected to output end B commonly. Output end C of the first inverter circuit and output end A are connected by capacity element C1 causing bootstrap effects. The gate electrode and the source of depletion-type auxiliary FETQB are connected to output end D of the second inverter circuit, and output signal OUT is generated at output end D. Electrode VDD where drains of FETQA1, QA3, QL1, QL2 and Q13 are connected supplies voltage +5V to the ground line (GND) where sources of FETQA2, QA4, QD1, and QD2 are connected. |
