| 摘要 |
PURPOSE:To reduce the oscillation frequency of VCO via the output of the continuous time detection circuit under the unlocked state in the PLL circuit. CONSTITUTION:Phase comparator 2 carries out a phase comparison between comparison frequency fr and output fv of programable divider 1. Output terminal U of comparator 2 delivers the O-level output in case the phase of frequency fv is lower than comparison frequency fr; and output terminal D delivers the O-level output in case fv features a faster phase respectively. And if the phase features an agreement, the 1-level output is delivered from both terminals D and U. The ouput of terminal D is applied to continuous time detection circuit 6 under the unlocked state via inverter 8 and then drives oscillation frequency control circuit 7 in case the unlocked state continues for a fixed time. The output of circuit 7 operates charge pump 3, and this output of pump 3 controls the oscillation frequency of VCO5 via LPF4. And the oscillation frequency of VCO5 reduces when terminal D features the O-level output. |
