RECONFIGURABLE VOLTAGE DESENSITIZATION CIRCUIT TO EMULATE SYSTEM CRITICAL PATHS

摘要

A circuit for controlling a clock signal may include a voltage source that provides a bias voltage, and at least one delay element having a non-linear capacitive load coupled to an output of the delay element. The non-linear capacitive load receives the bias from the voltage source and controls a delay magnitude applied to a plurality of pulses of the clock signal by the delay element. Based on the bias having a first scaled voltage, the delay magnitude that is applied to the plurality of clock pulses is increased in order to generate a frequency correction to the operating frequency of a microprocessor based on a variation to a microprocessor supply voltage. Based on the bias having a second scaled voltage, the delay magnitude that is applied to the clock pulses is maintained to retain the operating frequency of the clock during the variation to the supply voltage.

主权项

1. A circuit for controlling a clock signal having an operating frequency that is generated by a clock source associated with a microprocessor device, the circuit comprising:
a voltage source that provides a bias voltage; and at least one delay element having a non-linear capacitive load coupled to an output of the at least one delay element, the non-linear capacitive load receiving the bias voltage from the voltage source and controlling a delay magnitude applied to a plurality of pulses corresponding to the clock signal by the at least one delay element; and an edge detector circuit that receives both an undelayed version of the plurality of pulses corresponding to the clock signal and the plurality of pulses of the clock signal having the delay magnitude applied by the at least one delay element, wherein the edge detector circuit generates a multi-bit code based on the delay magnitude of the plurality of pulses of the clock signal relative to the undelayed version of the plurality of pulses corresponding to the clock signal, wherein, based on the bias voltage having a first scaled voltage, the delay magnitude that is applied to the plurality of pulses of the clock signal is increased in order to generate a frequency correction to the operating frequency based on a variation to a supply voltage of the microprocessor, and wherein, based on the bias voltage having a second scaled voltage, the delay magnitude that is applied to the plurality of pulses of the clock signal is maintained in order to retain the operating frequency of the clock signal during the variation to the supply voltage of the microprocessor.