| 摘要 |
PURPOSE:To enable to reset directly, by connecting the transistor Tr of reverse conducting type to the connection point between the transmission gate of the master and slave sections of delayed type FF and the inverter. CONSTITUTION:The master section consists of the transmission gate TG3 which turns on when the clock signal from the CL terminal is 0 and of the inveter IV4, and the slave section 2 consists of TG5 which turns on when the clock signal is 1 and the IV6. The n channel MOSFET 7 is connected between the connecting point A of TG5 and IV6 and the level 0, and P channel MOSFET 8 is connected between the connection point of TG5 and IV6 and the level 1. The gate of FET7 and FET8 is directly or via IV9 to the reset R terminal. FET7 and FET8 are conducted with the reset signal of the R terminal, the 0 or 1 level fed to the input of IV4 and IV6 is direclty reset, enabling to reset independently of the level of the clock signal at that time. |
