A system of functional units for performing logic functions.

摘要

According to the invention, the LSI testing methods allow the states of combinational logic networks to be captured in either a group of master latches (390) or slave latches (400) of shift registers used for performing scan-in/scan-out operations on test data (test patterns, result patterns), but not both,
<??>If on a particular test the states are captured in the master latches, then each master latch state is subsequently shifted to the corresponding slave latch by the application of a shift clock, as known from the art.
<??>If instead the states are captured in the slave latches the slave latches can be immediately shifted out for inspection.