| 发明名称 | Scaling EOT by eliminating interfacial layers from high-K/metal gates of MOS devices | ||
| 摘要 | An integrated circuit structure includes a semiconductor substrate, and a phonon-screening layer over the semiconductor substrate. Substantially no silicon oxide interfacial layer exists between the semiconductor substrate and the phonon-screening layer. A high-K dielectric layer is located over the phonon-screening layer. A metal gate layer is located over the high-K dielectric layer. | ||
| 申请公布号 | US9478637(B2) | 申请公布日期 | 2016.10.25 |
| 申请号 | US201012789681 | 申请日期 | 2010.05.28 |
| 申请人 | Taiwan Semiconductor Manufacturing Company, Ltd. | 发明人 | Xu Jeffrey Junhao |
| 分类号 | H01L29/78;H01L29/66;H01L21/28;H01L29/51;H01L21/02;H01L21/306 | 主分类号 | H01L29/78 |
| 代理机构 | Slater Matsil, LLP | 代理人 | Slater Matsil, LLP |
| 主权项 | 1. An integrated circuit structure comprising: a semiconductor substrate; a phonon-screening layer over the semiconductor substrate, wherein substantially no silicon oxide interfacial layer is between the semiconductor substrate and the phonon-screening layer; a high-K dielectric layer over the phonon-screening layer; and a metal gate layer over the high-K dielectric layer, wherein the phonon-screening layer, the high-K dielectric layer, and the metal gate layer are coterminous. | ||
| 地址 | Hsin-Chu TW | ||