| 摘要 |
PURPOSE:To enable to use the lower conversion frequency at modulation, and demodulation, by giving the specified phase relation to each clock supplied to the memory write-in control signal forming circuit and the memory readout control signal forming circuit. CONSTITUTION:The digital signal obtained through the conversion of analog signal with the PCM system is inserted to the set section of the signal of specified format such as video signal format and recorded in VTR8, and the reproduced digital signal is converted into analog signal. In this recording system, the clock obtained through the frequency-division 62' of the output of the crystal oscillation circuit 61' is fed to the memory write-in control signal forming circuit 64. Further, the clock frequency-divided at the circuit 64 is given to the PLL circuit 66 as the control signal. The clock obtained through the frequency division 63' of the output of the circuit 66 is fed to the memory readout control signal forming circuit 65. As a result, the phase of clock to the circuits 64 and 65 has a given relation to obtain the balance between the write-in and readout of the memory 5. |
