SISTEMA DI TEMPORIZZAZIONE TRIPLI TO PER IMPIANTI DUPLICATI CONTE NENTI CIRCUITI LOGICI,申请号IT19750070005-传众专利搜索

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发明名称	SISTEMA DI TEMPORIZZAZIONE TRIPLI TO PER IMPIANTI DUPLICATI CONTE NENTI CIRCUITI LOGICI
摘要
申请公布号	IT1051350(B)	申请公布日期	1981.04.21
申请号	IT19750070005	申请日期	1975.12.09
申请人	CSELT CENTRO STUDI E LABORATORI TELECOMUNICAZIONI S P A	发明人	MELINDO F;BELFORTE P
分类号	H04L7/00;(IPC1-7):G04G/	主分类号	H04L7/00
代理机构		代理人
主权项
地址

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