| 摘要 |
PURPOSE:To avoid the breakdown of the memory information caused by the malfunction during the unsteady operation of the CPU, by detecting the slope of the main power source having the slow rise and fall and then using this detected signal for the control signal. CONSTITUTION:The address terminals A0-A9 plus the data terminals D0-D3 of the CPU are connected to the RAM, and the data is stored into the RAM. The CMOSGATE which gates the output given from the Schmitt trigger circuit ST as well as the mode signal/write signal SR/W is connected to the RAM, and the signal is supplied to the R/W terminal of the RAM from the GATE. Then the trigger circuit ST detects the slope of the main power source having the slow rise and fall of the output VMP, and the signal detected by the circuit ST is applied to the GATE in the form of the control signal. Then the R/W terminal is set forcubly at H level, thus preventing the breakdown of the memory information of the RAM which is caused by the malfunction during the unsteady period of the CPU. |
