| 摘要 |
PURPOSE:To enable the common processing of circuits differing in speed by generating output data by sampling circuit data with sampling pulses faster than the timing of the circuit data and by generating a ready signal only once in each bit period. CONSTITUTION:Individual parts 2-1-2-n provided correspondingly to circuits 1-1-1-n consist of demodulator 11, data reproducing circuit 12, bit-synchronizing circuit 13, delay circuit 18, etc., respectively and an input signal is processed in series and inputted to common part 3. Demodulated signal (b) of input signal (a) to the individual part is passed through circuits 12 and 13 to generate bit-synchroniz ing signal (e), which is inputted to FFs 14 and 15. then, FF14 samples signal (b) with signal (e) to output signal (c) that synchronizes with the timing of the processor. With access signal (h) from common part 3, gate 16 is opened to output signal (c) as outpt data (d). Since the speed of signal (h) is set a little bit higher than that of signal (e), the misreading of data can be avoided. Signal (e) is delayed 18 and passed through FF15 and gate 17 to generate ready signal (g), by which a duplicated reading of data is prevented. |
