发明名称 SCRAMBLING SYSTEM
摘要 PURPOSE:To avoid an erroneous synchronism, by eliminating the same pattern as a scramble pattern or a frame synchronous pattern contained in the reverse signal of the scramble pattern. CONSTITUTION:An AND circuit G8 detects a combination of outputs of flip-flops Q1, Q2, Q3 and Q4 corresponding to the 15th bit in a scramble pattern that changes 0 to 1 to secure a pattern different from a frame synchronous pattern, and then produces 1. Then an OR is obtained for the outputs of AND circuits G7 and G8 through an OR circuit G9. Thus a scramble pattern with a prescribed alteration made on its output is obtained.
申请公布号 JPS56156045(A) 申请公布日期 1981.12.02
申请号 JP19800059031 申请日期 1980.05.02
申请人 FUJITSU LTD 发明人 SUZUKI EIJI
分类号 H04J3/06;H04L7/00;H04L7/08;H04L25/03 主分类号 H04J3/06
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