| 摘要 |
PURPOSE:To obtain an FET with a high withstand voltage eliminating increase in the area of the elements by providing one Schottky electrode on an n layer laid across two p layers on an n<-> type Si substrate. CONSTITUTION:P layers 12 are provided on an n<-> type Si substrate 11 at a given space and an n<+> layer 14 is made thereon. An n layer 14 is made on the surface of the substrate 11 adjacent to the facing surface of the layer 13 across the layer 12. A surface insulation film 15 is etched and one Schottky electrode 16 on the n layer 14 at a position cross the two p layers to make a first gate G1. A metal electrode 17 is provided and the electrode on the n<+> layer 13 is made source S and the electrode on the p layer 12 a second gate G2. A metal electrode 18 is provided on the back of the substrate to make a drain D. This enables a cascode connection of a Schottky type FET1 comprising the layer 13-G1-G2- the layer 14 and a junction type FET2 which comprises an n<-> layer between the two p layers 12 as channel and the electrode 18 as drain. The larger thickness of the substrate 11 can give a higher withstand voltage without increase in the area. |
